1. Field of the Invention
The present invention relates to the field of floating point dividers in microprocessors. Specifically, the present invention relates to quotient digit selection rules in Sweeny, Robertson, Tocher (SRT) division/square root implementations which prevent negative final partial remainders from occurring when results are exact, and which provide support for correct rounding in all rounding modes.
2. Discussion of the Related Art
The SRT algorithm provides one way of performing non-restoring division. See, J. E. Robertson, "A new class of digital division methods," IEEE Trans. Comput., vol. C-7, pp. 218-222, September 1958, and K. D. Tocher, "Techniques of multiplication and division for automatic binary computers," Quart. J. Mech. Appl. Math., vol. 11, pt. 3, pp. 364-384, 1958. Digital division takes a divisor and a dividend as operands and generates a quotient as output. The quotient digits are calculated iteratively, producing the most significant quotient digits first. In SRT division, unlike other division algorithms, each successive quotient digit is formulated based only on a few of the most significant partial remainder digits, rather than by looking at the entire partial remainder, which may have a very large number of digits. Since it is not possible to insure correct quotient digit selection without considering the entire partial remainder in any given iteration, the SRT algorithm occasionally produces incorrect quotient digit results. However, the SRT algorithm provides positive, zero, and negative quotient digit possibilities. If the quotient digit in one iteration is overestimated, then that error is corrected the next iteration by selecting a negative quotient digit. In SRT division, quotient digits must never be underestimated; quotient digits must always be overestimated or correctly estimated. By never underestimating any quotient digits, the partial remainder is kept within prescribed bounds so as to allow the correct final quotient to be computed. Because the SRT algorithm allows negative quotient digits, the computation of the final quotient output usually involves weighted adding and subtracting of the quotient digits, rather than merely concatenating all the quotient digits as in normal division.
The higher the radix, the more digits of quotient developed per iteration but at a cost of greater complexity. A radix-2 implementation produces one digit per iteration; whereas a radix-4 implementation produces two digits per iteration. FIG. 1 illustrates a simple SRT radix-2 floating point implementation. The simple SRT radix-2 floating point implementation shown in FIG. 1 requires that the divisor and dividend both be positive and normalized; therefore, 1/2.ltoreq.D, Dividend &lt;1. The initial shifted partial remainder, 2PR0!, is the dividend. Before beginning the first quotient digit calculation iteration, the dividend is loaded into the partial remainder register 100; thus, the initial partial remainder is the dividend. Subsequently, the partial remainders produced by iteration are developed according to the following equation. EQU PR.sub.i+1 =2PR.sub.i -q.sub.i+1 D (1)
In Equation 1, q.sub.i+1 is the quotient digit, and has possible values of -1, 0, or +1. This quotient digit q.sub.i+1 is solely determined by the value of the previous partial remainder and is independent of the divisor. The quotient selection logic 102 takes only the most significant four bits of the partial remainder as input, and produces the quotient digit. In division calculations, the divisor remains constant throughout all iterations. However, square root calculations typically involve adjustments to the divisor stored in the divisor register 101 after each iteration. Therefore, the independence of the quotient digit selection on the divisor is an attractive feature for square root calculations.
The partial remainder is typically kept in redundant carry save form so that calculations of the next partial remainder can be performed by a carry-save adder instead of slower and larger carry-propagate adders. The partial remainder is converted into non-redundant form after all iterations have been performed and the desired precision has been reached. Because the SRT algorithm allows overestimation of quotient digits resulting in a negative subsequent partial remainder, it is possible that the last quotient digit is overestimated, so that the final partial remainder is negative. In that case, since it is impossible to correct for the overestimation, it is necessary to maintain Q and Q-1, so that if the final partial remainder is negative, Q-1 is selected instead of Q. The quotient digits are normally also kept in redundant form and converted to non-redundant form at the end of all iterations. Alternatively, the quotient and quotient minus one (Q and Q-1) can be generated on the fly according to rules developed in M. D. Ercegovac and T. Lang, "On-the-fly rounding," IEEE Trans. Comput., vol. 41, no. 12, pp. 1497-1503, December 1992.
The SRT algorithm has been extended to square root calculations allowing the utilization of existing division hardware. The simplified square root equation looks surprisingly similar to that of division. See, M. D. Ercegovac and T. Lang, "Radix-4 square root without initial PLA," IEEE Trans. Comput., vol. 39, no. 8, pp. 1016-1024, August 1990. The iteration equation for square root calculations is as follows. EQU PR.sub.i+1 =2PR.sub.i -q.sub.i+1 (2Q.sub.i +q.sub.i+1 2.sup.-(i+1))(2)
In Equation 2, the terms in parentheses are the effective divisor. For square root calculations, the so-called divisor is a function of Qi, which is a function of all the previous root digits q1 through qi. The root digits hereinafter will be referred to as "quotient digits" to maintain consistency in terminology. Therefore, in order to support square root calculation using the same hardware as used for division, on-the-fly quotient generation is required in order to update the divisor after each iteration.
Binary division algorithms are analogous to standard base 10 long division which is taught in grammar school. In R/D=Q, each quotient digit for Q is guessed. In order to determine the first quotient digit, a guess for the proper quotient digit is multiplied by the divisor, and that product is subtracted from the dividend to produce a remainder. If the remainder is greater than the divisor, the guess for the quotient digit was too small; if the remainder is negative, the guess for the quotient digit was too large. In either case, when the guess for the quotient digit is incorrect, the guess must be changed so that the correct quotient digit is derived before proceeding to the next digit. The quotient digit is correct when the following relation is true: 0.ltoreq.PR&lt;D, in which PR stands for the partial remainder after subtraction of the quotient digit multiplied by the divisor.
The key to the SRT division algorithm is that negative quotient digits are permitted. For example, in base 10, in addition to the standard digits 0 through 9, quotient digits may take on values of -1 through -9. Consider the division operation 600.div.40. If the correct quotient digits are selected for each iteration, the correct result is 15. However, assume for the moment that during the first iteration, a quotient digit of 2 was incorrectly guessed instead of the correct digit of 1. The partial remainder after 2 has been selected as the first quotient digit is 600-(2*40*10.sup.1)=-200. According to SRT division, this error can be corrected in subsequent iterations, rather than having to back up and perform the first iteration again. According to SRT division, assume that the second quotient digit is correctly guessed to be -5. The partial remainder after that iteration will be -200-(-5*40*100)=0. When the partial remainder after an iteration is zero, the correct values for all the remaining digits are zeros. Thus, the computed result is 2*10.sup.1 +-5*10.sup.0 =15, which is the correct result. The SRT algorithm thus allows an overestimation of any given quotient digit to be corrected by the subsequent selection of one or more negative quotient digits. It is worth noting that the estimated quotient digit must not be more than one greater than the correct quotient digit in order to subsequently reduce the partial remainder to zero, thus computing the correct result. If errors greater than positive one were allowed in estimating quotient digits, then quotient digits less than -9 (for example -10, -11, etc.) would be required in base 10. Similarly, since the range of quotient digits is not expanded in the positive direction at all according to the SRT algorithm, underestimation of the correct quotient digit is fatal, because the resulting partial remainder will be greater than the divisor multiplied by the base, and a subsequent quotient digit higher than 9 (for example 10, 11, etc.) in base 10 would be required. Therefore, in order to keep the partial remainder within prescribed bounds, the quotient digit selection must never underestimate the correct quotient digit, and if it overestimates the quotient digit, it must do so by no more than one.
It is possible to guarantee that the above criteria for keeping the partial remainder within prescribed bounds will be satisfied without considering all the partial remainder digits. Only a few of the most significant digits of the partial remainder must be considered in order to choose a quotient digit which will allow the correct result to be computed.
SRT division requires a final addition after all quotient digits have been selected to reduce the redundant quotient representation into standard non-redundant form having only non-negative digits.
In binary (base 2) which is utilized in modern electrical computation circuits, SRT division provides quotient digits of +1, 0, or -1. The logic 102 which generates quotient selection digits is the central element of an SRT division implementation. Early research indicated that only the most significant three bits of redundant partial remainder are necessary inputs for a radix-2 quotient digit selection function. (See, S. Majerski, "Square root algorithms for high-speed digital circuits," Proc. Sixth IEEE Symp. Comput. Arithmetic., pp. 99-102, 1983; and D. Zuras and W. McAllister, "Balanced delay trees and combinatorial division in VLSI," IEEE J. Solid-State Circuits., vol. SC-21, no. 5, pp. 814-819, October 1986.) However more recent studies have shown that four bits are required to correctly generate quotient digit selection digits and keep the partial remainder within prescribed bounds. (See M. D. Ercegovac and T. Lang, Division and Square Root: Digit-recurrence Algorithms and Implementations, Kluwer Academic Publishers, 1994, ch. 3; S. Majerski, "Square-rooting algorithms for high-speed digital circuits," IEEE Trans. Comput., vol. C-34, no. 8, pp. 724-733, August 1985; P. Montuschi and L. Ciminiera, "Simple radix 2 division and square root with skipping of some addition Steps," Proc. Tenth IEEE Symp Comput. Arithmetic. pp. 202-209, 1991; and V. Peng, S. Samudrala, and M. Gavrielov, "On the implementation of shifters, multipliers, and dividers in floating point units," Proc. Eighth IEEE Symp. Comput. Arithmetic, pp. 95-101, 1987. The selection rules according to the prior art can be expressed as in the following equations in which PR represents the most significant four bits of the actual partial remainder, and in which the decimal point appears between the third and fourth most significant digits. The partial remainder is in two's complement form, so that the first bit is the sign bit.
q.sub.i+1 =1, if 0.ltoreq.2PRi!.ltoreq.3/2, PA1 q.sub.i+1 =0, if 2PRi!=-1/2, PA1 q.sub.i+1 =-1, if -5/2.ltoreq.2PRi!.ltoreq.-1.
Because the partial remainder is stored in register 100 in carry-save form, the actual most significant four bits are not available without performing a full carry propagate addition of the carry and sum portions of the partial remainder. Because it is desirable to avoid having to perform a full carry propagate addition during each iteration in order to compute the most significant four bits of the partial remainder, quotient digit selection rules can be developed using an estimated partial remainder.
The estimated partial remainder (PR.sub.est) is computed using only a four-bit carry propagate adder that adds the most significant four bits of the carry and sum portions of the actual partial remainder. This simplification represents a significant savings of latency because the equivalent of a full 59 bit carry propagate addition would otherwise be required to compute the actual most significant four bits of the partial remainder. The estimated partial remainder PR.sub.est does not reflect the possibility that a carry might propagate into the bit position corresponding to the least significant bit position of the estimated partial remainder if a full 59-bit carry propagate addition had been performed. The truth table below describes the quotient selection rules according to the prior art where the most significant four bits of the estimated partial remainder are used to select the correct quotient digit. Thus, the truth table below takes into consideration the fact that the most significant four bits of the true partial remainder may differ from the most significant four bits of the estimated partial remainder.
TABLE I ______________________________________ Truth Table for Prior Art Radix-2 Quotient Selection 2PRi!.sub.estimated quotient digit Comments ______________________________________ 100.0 don't care 2PR never &lt; -5/2 100.1 don't care 2PR never &lt; -5/2 101.0 -1* 2PR never &lt; -5/2, but 2PR could be 101.1 when 2PR.sub.est is 101.0 101.1 -1 110.0 -1 110.1 -1 111.0 -1 2PR could = 111.1 111.1 0 2PR could = 000.0 000.0 +1 000.1 +1 001.0 +1 001.1 +1 010.0 don't care 2PR never &gt; 3/2 010.1 don't care 2PR never &gt; 3/2 011.0 don't care 2PR never &gt; 3/2 011.1 don't care 2PR never &gt; 3/2 ______________________________________
In the above truth table, the four bits representing 2PR.sub.est are a non-redundant representation of the most significant four carry and sum bits of the partial remainder. The fourth bit is the fraction part, so that the resolution of the most significant four bits of the partial remainder is 1/2.
The quotient selection logic is designed to guess correctly or overestimate the true quotient result, e.g. predicting 1 instead of 0, or 0 instead of -1. The SRT algorithm corrects itself later if the wrong quotient digit has been chosen.
The prior art truth table for SRT radix-2 quotient selection logic has several don't care inputs because the partial remainder is constrained to -5/2.ltoreq.2PRi!.ltoreq.3/2. The estimated partial remainder is always less than or equal to the true most significant bits of the partial remainder because the less significant bits are ignored. Therefore, there is a single case (marked with an asterisk in the above table) where the estimated partial remainder appears to be out of bounds. By construction, the real partial remainder is within the negative bound because the SRT algorithm as implemented will never produce an out of bounds partial remainder, so -1 is the appropriate quotient digit to select. There are two other cases (those corresponding to the entries for 111.0 and 111.1 in Table I) in which the quotient digit selected based on the estimated partial remainder differs from what would be chosen based on the real partial remainder. However, in both of these instances of "incorrect" quotient digit selection, the quotient digit is not underestimated and the partial remainder is kept within prescribed bounds, so that the final result will still be generated correctly.
The following table II illustrates the quotient selection logic described in Table I in a simplified form. In the table below, an "x" represents a "don't care" logic variable. Obviously, the third case, in which 1xx.x produces a -1 quotient digit does not apply when the estimated partial remainder is 111.1, such that the second entry applies, and the correct quotient digit is 0.
TABLE II ______________________________________ Simplified Prior Art QSLC Truth Table 2PRi!.sub.estimated quotient digit.sub.i+1 ______________________________________ 0xx.x +1 111.1 0 1xx.x -1 ______________________________________
Floating point operations generate a sticky bit along with the result in order to indicate whether the result is inexact or exact. When the result is inexact, the sticky bit is asserted; conversely, when the result is exact, the sticky bit is deasserted. Essentially, the sticky bit indicates whether or not any of the bits of less significance are non-zero. The sticky bit is also used with the guard and round bits for rounding according to IEEE Standard 754. See, "IEEE standard for binary floating-point arithmetic," ANSI/IEEE Standard 754-1985, New York, The Institute of Electrical and Electronic Engineers, Inc., 1985.
For divide and square root operations, the sticky bit is determined by checking if the final partial remainder is non-zero. The final partial remainder is defined as the partial remainder after the desired number of quotients bits have been calculated. Since the partial remainder is in redundant form, a carry-propagate addition is performed prior to zero-detection. A circuit for computing the sticky bit is shown in FIG. 2. In FIG. 2, the carry 201 and sum 202 portions of the final partial remainder are added together by the carry propagate adder 200. The most significant bit output by the adder 200 is the sign bit 203 of the final partial remainder. As illustrated in FIG. 1, the division hardware accumulates the quotient Q and the quotient minus one Q-1. When the final partial remainder is negative, Q-1 is the proper quotient; when the final partial remainder is zero or positive, Q is the correct quotient. Thus, the sign bit 203 is used to select the correct quotient. Referring again to FIG. 2, the zero detector 204 determines if all bits of the non-redundant final partial remainder 205 are zeros and outputs a the sticky bit 206. The zero detector 204 is logically equivalent to a large 59-input OR gate.
At first glance, the above solution seems perfectly reasonable for all final partial remainder possibilities, positive or negative. However, in the rare case in which the result is exact, the final partial remainder will be equal to the negative divisor. For example, consider a number divided by itself, as illustrated in the table below, in which PRi! represents the partial remainder after the ith quotient digit has been selected.
TABLE III ______________________________________ Division iterations for a number divided by itself ______________________________________ PR0!= Init dividend/2 = D/2 q1!=+1 Q=1 Q-1=0 PR1!= 2(D/2) - ( 1)D = 0 q2!=+1 Q=11 Q-1=10 PR2!= 2(0) - ( 1)D = -D q3!=-1 Q=101 Q-1=100 PR3!= 2(-D) - (-1)D = -D q4!=-1 Q=1001 Q-1=1000 PRn!= 2(-D) - (-1)D = -D q5!=-1 Q=100..001 Q-1=100..000 ______________________________________
Since the dividend is always positive and normalized, the quotient digit from the first iteration is one. This is a consequence of the fact that a positive normalized number has a sign bit of zero and a most significant digit of one. When a positive normalized number is divided by two, presumably by right shifting by one bit position, the most significant bit necessarily becomes a zero. (If a negative number is divided by two, the most significant bit is one, because the most significant bits are sign extended so as to match the sign bit giving the correct two's complement representation.) When the most significant bit is a zero, Table II above dictates that a quotient digit of one should be selected.
For the second iteration shown in Table III, the partial remainder PR1! is zero which causes the second quotient digit to be one. For all subsequent iterations, the partial remainder will equal the negative divisor and quotient digits of minus one will be selected. After the last iteration, performing a sign detect on the final partial remainder PRn! determines that the final partial remainder is negative and indicates that Q-1 should be chosen. This is in fact the correct result. However, this same final partial remainder is non-zero which erroneously suggests an inexact result and erroneously suggests that the sticky bit should be asserted.
This problem extends to any division operation for which the result should be exact. Fundamentally, the problem is a consequence of the fact that the quotient selection logic is defined to guess positive for a zero partial remainder and correct for it later, as illustrated by Table II. The prior art dividers require one processor cycle for restoration of negative final partial remainders prior to sticky bit calculation. To insure correct rounding, it is necessary to correctly compute the sticky bit. It would be advantageous to develop a divider which did not restore negative final partial remainders, but that could nevertheless guarantee correct computation of the sticky bit.